1. Field of the Invention
The present invention relates to a method for forming a planarized layer of a semiconductor device. More particularly, the present invention relates to a method for forming a planarized layer of a semiconductor device, which can effectively planarize an insulation film at an edge portion of an underlying pattern corresponding to a high step when the insulation film is formed to cover the underlying pattern having a predetermined height.
2. Description of the Related Art
As semiconductor devices become more highly integrated, the area of a unit cell of the semiconductor device becomes smaller. Capacitors having a cylindrical shape are therefore often employed in order to ensure the delivery of required capacitance in the smaller area. To increase the capacitance of the capacitor, the height of the capacitor is made higher, thereby generating a high step between the cell and the peripheral regions of a semiconductor substrate.
Because the step formed between the cell and the peripheral regions is high, a metal bridge or a metal stringer may remain in a successive metal process, causing a failure of metal wiring in the semiconductor device. In addition, a sufficient processing margin for a photolithography process cannot be ensured at the boundary between the cell and the peripheral regions where the step is positioned. As a result, various problems may arise in designing and manufacturing the semiconductor device.
To reduce the slope of the boundary between the cell and the peripheral regions, after an insulation film is coated on the semiconductor substrate, the coated insulation film is generally thermally treated to re-flow the insulation film, thereby reducing the slope of the boundary. However, only the slope of the boundary where the step is positioned decreases, the absolute step of the insulation film between the cell and the peripheral regions does not decrease. Therefore, re-flowing the insulation film is not sufficient to reduce the step between the cell and the peripheral regions when the step is high enough.
To overcome the above-mentioned problem, a chemical-mechanical polishing (CMP) process has been developed to remove a portion of an insulation film in a cell region having a height relatively higher than another portion of the insulation film in a peripheral region. The CMP process is intended to reduce the height of the portion of the insulation film in the cell region to make it equal to the height of the portion of the insulation film in the peripheral region. Although a CMP process can remove the step between the cell and the peripheral regions, this process takes a long time because the portion of the insulation film in the cell area has a much larger area than the portion of the insulation film in the peripheral region.
Therefore, to effectively remove a global step by a CMP process, several methods have been proposed in which an insulation film enclosed within a pillar remaining at a boundary between a cell region and a peripheral region is primarily removed by a predetermined depth through a photolithography and etching process prior to removal of the pillar by the CMP process. As a result, the amount of time required for the CMP process to planarize the insulation film may be reduced.
However, a better method is still needed to effectively remove a global step between a cell region and a peripheral region of a semiconductor device.